The present invention relates to on-chip circuits that permit high speed testing of memory of, for example, a Synchronous Dynamic Random Access Memory (SDRAM) or a Rambus dynamic memory using a currently available external memory tester operating at a speed slower than the higher operating speeds of the SDRAMs.
In the manufacturing of a new Dynamic Random Access Memory (DRAM) chips, a DRAM chip is generally subjected to various tests to ensure proper operation thereof when subsequently used. In the prior art, DRAM chips are tested with a memory tester and/or burn-in (BI) oven which are readily available from various vendors and are well-known in the art. In a burn-in test, the DRAM chip is heated in an oven so that the chip and it components may be subjected to stress to detect any possible failures that could occur during normal operating conditions. It may be found that during a burn-in test, internal voltages may be altered to follow any rise in an applied external voltage. Such new DRAM chips such as, for example, a Synchronous Dynamic Random Access Memory (SDRAM) or a Rambus dynamic memory, have high speed interface having speeds of 100 MHz to 1 GHz. The problem with the prior art testing apparatus is that the current memory testers and Burn-In ovens can only deliver test speeds of from 5 MHz to 200 MHz which only covers a small portion of the lower speeds used by the new DRAMs.
It is desirable to provide testing apparatus that at least covers the gap between the speeds found with the new DRAMs and the currently available test equipment so that the DRAMs can be tested at their maximum speeds.
The present invention is directed to on-chip circuits that permit high speed testing of memories on, for example, a Synchronous Dynamic Random Access Memory (SDRAM) chip or a Rambus dynamic memory chip using a currently available external memory tester operating at a speed slower than the higher operating speeds of the SDRAMs.
Viewed from a first apparatus aspect, the present invention a semiconductor body comprising a first portion comprising a memory system, and a second portion comprising a programmable clock and test command signal generator. The programmable clock and test command signal generator comprises a programmable clock signal generator, a counter, and a programmable look-up memory. The programmable clock signal generator comprises a clock input terminal and an output terminal, and is designed to generate at the output terminal thereof a clock output signal having a frequency which is a selective predetermined multiple of an external clock signal applied to the clock input terminal. The counter has an input coupled to the output terminal of the programmable clock signal generator and at least one output terminal. The counter is designed to generate at the at least one output terminal thereof a cyclical binary count comprising a number of counts corresponding to the multiple of the frequency of the external clock output signal generated by the programmable clock signal generator. The programmable look-up memory comprises memory locations for storing separate commands useful for testing predetermined sections of the memory system. The programmable look-up memory further comprises (a) at least one first input terminal coupled to receive the cyclical binary count from the counter, (b) a plurality of second input terminals coupled to receive remotely generated encoded binary address input signals which are combined with the binary count from the counter to access predetermined memory locations in the look-up memory, and (c) at least one output terminal coupled to predetermined inputs of the memory system such that testing of the memory system is accomplished at the speed of the output clock signal from the programmable clock signal generator.
Viewed from a second apparatus aspect, the present invention is a memory chip comprising a first portion comprising a memory system, and a second portion comprising a programmable clock and test command signal generator. The programmable clock and test command signal generator comprises a programmable delay locked loop (DLL), a counter, and a programmable look-up memory. The programmable delay locked loop (DLL) comprises a clock input terminal and an output terminal. The DLL is designed to generate at the output terminal thereof a clock output signal having a frequency which is a selective predetermined multiple of an external clock signal applied to the clock input terminal. The counter has an input coupled to the output terminal of the DLL and at least one output terminal The counter is designed to generate, at the at least one output terminal thereof, a cyclical binary count comprising a number of counts corresponding to the multiple of the frequency of the external clock output signal generated by the DLL. The programmable look-up memory comprises a plurality of memory locations for storing separate commands useful for testing predetermined sections of the memory system. The programmable look-up memory comprises (a) at least one first input terminal coupled to receive the cyclical binary count from the counter, (b) a plurality of second input terminals coupled to receive remotely generated encoded binary address input signals which are combined with the binary count from the counter to access predetermined memory locations in the look-up memory, and (c) at least one output terminal coupled to predetermined inputs of the memory system such that testing of the memory system is accomplished at the speed of the output clock signal from the DLL.
Viewed from a method aspect, the present invention is a method of testing a semiconductor body having a memory system in a first portion thereof, and a programmable clock and test command signal generator in a second portion thereof. With the method, an output clock signal is selectively generated at an output of a programmable clock signal generator in the programmable clock and test command signal generator having a frequency which is a predetermined multiple of a received external clock signal at an input of the programmable clock signal generator. An output signal is generated at an output of a counter comprising a cyclical binary count comprising a number of counts corresponding to the predetermined multiple of the received external clock signal selectively generated by the programmable clock signal generator in response to the output clock signal received at an input from the programmable clock signal generator. Separate commands for testing the memory system are stored in a programmable look-up memory comprising a plurality of memory locations. The plurality of memory locations in the programmable look-up memory are addressed with each of (1) selective external binary encoded address signals received at a plurality of first input terminals thereof where each separate binary encoded external address signal is used for accessing a separate predetermined section of the memory locations, and (2) output signal from the counter receiver at at least one second input terminals for sequentially accessing separate memory locations within the addressed separate predetermined section of memory locations at the speed of the output clock signal from the programmable clock signal generator.